1. Field of the Invention
The present application relates to an array substrate including a thin film transistor having an oxide semiconductor layer and a method of fabricating the array substrate.
2. Discussion of the Related Art
Display devices such as liquid crystal display (LCD) devices or electroluminescent display (ELD) devices having a light weight, thin profile, and low power consumption have replaced cathode ray tube (CRT) devices. Among the LCD devices, the active matrix LCD (AM-LCD) devices use switching elements and pixel electrodes arranged in a matrix structure and have high resolution and superior suitability for displaying moving images.
In addition, organic electroluminescent display (OELD) devices are an emissive type display and have a high brightness and low driving voltage. The OLED devices also have advantages such as a high contrast ratio, ultra thin profile, short response time of about several microseconds, wide viewing angle and stability at low temperature. For example, the OLED devices can be driven with a driving voltage of about 5V DC to about 15V DC.
In addition, the LCD OLED devices include an array substrate having a thin film transistor as a switching element for a pixel region. For example, FIG. 1 is a cross-sectional view illustrating a related art array substrate. The related art array substrate shown in FIG. 1 includes a gate line (not shown) and a gate electrode 15 formed in a pixel region P on a substrate 11, and a gate insulating layer 18 formed on the gate line and the gate electrode 15. Also included is a semiconductor layer 28 including an active layer 22 of intrinsic amorphous silicon and an ohmic contact layer 26 of impurity-doped amorphous silicon formed on the gate insulating layer 18 over the gate electrode 15. Source and drain electrodes 36 and 38 spaced apart from each other are also formed on the ohmic contact layer 26.
Further, the gate electrode 15, the gate insulating layer 18, the semiconductor layer 28, the source electrode 36 and the drain electrode 38 constitute a thin film transistor (TFT) Tr. In addition, a passivation layer 42 is formed on the TFT Tr and has a drain contact hole 45 exposing the drain electrode 38. A pixel electrode 50 is also formed on the passivation layer 42 in the pixel region P, and the pixel electrode 50 is connected to the drain electrode 38 through the drain contact hole 45.
A data line 33 including patterns 20 (i.e., first and second patterns 27 and 23) are then formed on the substrate 11 and crosses the gate line to define the pixel region P. The first and second patterns 27 and 23 also have the same layers as the ohmic contact layer 26 and the active layer 22, respectively. Further, the active layer 22 of the semiconductor layer 28 has a first portion exposed through the ohmic contact layer 26 and a second portion under the ohmic contact layer 26. The first and second portions of the active layer 22 also have first and second thicknesses t1 and t2 that are different from each other (t1≠t2). The thickness difference of the active layer 22 results from a fabrication method and causes a degradation in the characteristic of the TFT Tr.
Next, FIGS. 2A to 2E are cross-sectional views showing a process of forming a semiconductor layer, a source electrode and a drain electrode on an array substrate for a related art display device. In addition, a gate electrode and a gate insulating layer between the array substrate and the semiconductor layer are omitted in FIGS. 2A to 2E. As shown in FIG. 2A, an intrinsic amorphous silicon layer 20, an impurity-doped silicon layer 24 and a metal layer 30 are sequentially formed on the substrate 11. After a photo resist (PR) layer is formed on the metal layer 30, light is irradiated onto the PR layer using a photo mask to form a first PR pattern 91 corresponding to the source and drain electrodes and a second PR pattern 92 corresponding to the first portion exposed through the source and drain electrodes 36 and 38 in FIG. 1. The first and second PR patterns 91 and 92 also have third and fourth thicknesses t3 and t4 in which the fourth thickness is smaller than the third thickness (t4<t3).
Also, in FIG. 2B, the metal layer 30, the impurity-doped silicon layer 24 and the intrinsic amorphous silicon layer 20 in FIG. 2A are etched using the first and second PR patterns 91 and 92 as an etching mask so that a source-drain pattern 31, an impurity-doped amorphous silicon pattern 25 and the active layer 22 can be formed. In FIG. 2C, the second PR pattern 92 in FIG. 2C is removed and the first PR pattern 91 in FIG. 2C is partially removed through an ashing process so that a third PR pattern 93 having a reduced thickness can be formed on the source-drain pattern 31.
Further, in FIG. 2D, the source-drain pattern 31 in FIG. 2C is etched using the third PR pattern 93 as an etching mask so that the source and drain electrodes 36 and 38 can be formed and the impurity-doped amorphous silicon pattern 25 can be exposed between the source and drain electrodes 36 and 38. In FIG. 2E, the impurity-doped amorphous silicon pattern 25 in FIG. 2D exposed between the source and drain electrodes 36 and 38 is etched through a dry etching step so that the ohmic contact layer 26 can be formed under the source and drain electrodes 36 and 38. When the dry etching step is performed for an insufficient time, the impurity-doped amorphous silicon pattern 25 remains on the active layer 22 between the source and drain electrodes 36 and 38.
The remaining impurity-doped amorphous silicon pattern 25 also connects the source and drain electrodes 36 and 38 to deteriorate the TFT Tr in FIG. 1. Thus, to remove the impurity-doped amorphous silicon pattern 25 exposed between the source and drain electrodes 36 and 38 completely, the dry etching step is performed for a sufficiently long time. Accordingly, the active layer 22 under the impurity-doped amorphous silicon pattern 25 exposed between the source and drain electrodes 36 and 38 is partially etched.
As a result, the first portion of the active layer 22 exposed through the ohmic contact layer 26 has the first thickness t1 and the second portion of the active layer 22 under the ohmic contact layer 26 has the second thickness t2 different from the first thickness t1 (t1≠t2). Also, the thickness difference of the active layer 22 causes degradation in the characteristic of the TFT Tr in FIG. 1. In addition, since the active layer 22 is partially removed during the drying etching step for the ohmic contact layer 26, the intrinsic amorphous silicon layer 20 in FIG. 2A is formed to have a thickness, for example, within a range of about 1500 Å to about 1800 Å. Accordingly, the deposition time for the intrinsic amorphous silicon layer 20 in FIG. 2A increases and the productivity is reduced.